1. Field of the Invention
The present invention relates to an Electron Emission Display (EED) with decreased signal distortion and a method of driving the EED, and more particularly, to an EED which can compensate for waveform distortion or signal delay caused by the impedance of an electrode line during a blanking period just before a display data signal is outputted, and a method of driving the EED.
2. Description of the Related Art
An EED includes an EED panel and a driver. When the driver supplies a positive voltage to an anode electrode of the EED panel, if a positive voltage is supplied to a gate electrode and a negative voltage is supplied to a cathode electrode, electrons are emitted from the cathode electrode. The emitted electrons are accelerated toward the gate electrode and converged into the anode electrode. Then, the electrons collide with fluorescent cells disposed in front of the anode electrode, thereby emitting light.
The gate electrodes and the cathode electrodes can be respectively used as scan electrodes and data electrodes, and vice versa.
An EED includes an EED panel and a driver. The driver includes a video processor, a panel controller, a scan driver, a data driver, and a power supply unit.
The video processor converts an external analog video signal into a digital signal to generate an internal video signal, for example, R, G and B video data, a clock signal, and horizontal and vertical synchronization signals.
The panel controller generates data driving control signals and scan driving control signal according to the internal video signal outputted from the video processor. The data driver processes the data driving control signal and generates a display data signal to data electrode lines of the EED panel. The data electrode lines can use cathode electrode lines or gate electrode lines. The scan driver processes the scan driving control signal and supplies the processed signal to scan electrode lines. The scan electrode lines can use the gate electrode lines or the cathode electrode lines.
The power supply unit supplies power to the video processor, the panel controller, the scan driver, the data driver, and an anode electrode of the EED panel.
The operation of the EED is as follows.
It is assumed that the data electrode lines are connected to the cathode electrodes of the EED panel and the scan electrode lines are connected to gate electrodes. A positive voltage is supplied to the anode electrode if a positive voltage is supplied to the gate electrodes through the scan electrode lines and a negative voltage is supplied to the cathode electrodes through the data electrode lines, resulting in electrons being emitted by the cathode electrodes. The emitted electrons are accelerated toward the gate electrodes and converged into the anode electrodes. Then, the electrons collide with fluorescent cells disposed in front of the anode electrodes, thereby emitting light. Alternatively, the data electrode lines and the scan electrode lines can be respectively connected to the gate electrodes and the cathode electrodes.
Gray level control methods for adjusting luminance of the EED panel include a Pulse Width Modulation (PWM) scheme which controls an applying time of data signal pulses and a Pulse Amplitude Modulation (PAM) scheme which controls a voltage amplitude of data signal pulses. According to the PWM scheme, the panel controller generates gray scale signals depending on gray scale information included in the video data. The data driver modulates the pulse width of the data driving signal included in the data driving control signal, depending on the gray scale signals. Then, the PWM-ed signal is boosted to a voltage at which the panel electrodes can be driven, such that the resultant display data signal is outputted to the data electrode lines. According to the PAM scheme, the data driver modulates the pulse amplitude of the data driving signal included in the data driving control signal, depending on the gray scale signals. Then, the PAM-ed signal is boosted to a voltage at which the panel electrodes can be driven, such that the resultant display data signal is outputted to the data electrode lines.
When the display data signal is supplied to the gate electrode lines, a positive display data signal having a voltage Vc exceeding a emission start voltage Vth is supplied at a time point t1 and is ended at a time point t2. Accordingly, electrons must be emitted from the data electrodes at the time point t1.
However, the EED panel has impedance components, such as resistance and capacitance of the electrode lines, depending on environment factors or materials in the manufacturing processes. Thus, pulse waveforms of the data signals or the scan signals supplied to the EED panel can be distorted or delayed. Due to the pulse delay, the luminance of pixels receiving the display data signals can be degraded. Since different luminance is outputted according to the impedance components, the luminance between the pixels receiving the same data signals can also be different.
Due to the delay of the display data signal, the emission start time point is delayed from t1 to t1′, and the emission end time point is delayed from t2 to t2′. Energy represented by an area “A1” is not outputted by the EED panel, and an unintended energy represented by an area “A2” is outputted. Since the energy A1 is larger than the energy A2, the luminance emitted by the EED panel is degraded.
A technology for solving the delay and distortion of the display data signal is discussed in Japanese Laid-Open Patent Publication No. 1995/181916. In this patent, a voltage selector is installed within a data driver. The voltage selector additionally modulates a pulse amplitude of a PWM-ed data signal, such that luminance information is added to the PWM-ed data. Thus, the luminance of the panel is increased and the signal delay is reduced. However, when the modulation level of the PAM is large, a fine voltage modulation is still difficult.
In Korean Laid-Open Patent Publication No. 1998/0082973, a negative (−) tab voltage is supplied at a falling edge of a scan voltage, such that a falling width of a scanning voltage becomes large. As a result, a delay time is reduced. However, due to the variation in the amplitude of the voltage, the luminance can be changed differently unlike the purpose of the developer.
Also, U.S. Laid-Open patent Publication No. 2004/0004588 discusses a compensation circuit. In this patent, considering that a emission current is reduced as a time elapses, a gate electrode is driven with a voltage higher than a drive voltage of a reference level, and a FET is coupled to a cathode electrode so that a current greater than a desired current cannot flow. However, since the luminance according to the gray level outputted from a panel is nonlinear with respect to a emission current and a drive voltage, it is impossible to adaptively compensate for a correct drive voltage for outputting a desired luminance. Also, when an excessive drive voltage is supplied to a data electrode, an electron emission source can be easily degraded and the life-span of the device can be shortened.
In Korean Laid-Open Patent Publication No. 1999/0026581, during a predetermined period before a data voltage outputted from a data driver is supplied to each pixel of a panel, a voltage charged at a pixel is previously charged or discharged using a redundant capacitor, such that a time taken to charge a pixel with a data voltage is reduced.